专用集成电路时程序验证
2009-11
清华大学出版社
内库加
189
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微电子技术是信息科学技术的核心技术之一，微电子产业是当代高新技术产业群的核心和维护国家主权、保障国家安全的战略性产业。我国在《信息产业“十五”计划纲要》中明确提出：坚持自主发展，增强创新能力和核心竞争力，掌握以集成电路和软件技术为重点的信息产业的核心技术，提高具有自主知识产权产品的比重。发展集成电路技术的关键之一是培养具有国际竞争力的专业人才。 微电子技术发展迅速，内容更新快，而我国微电子专业图书数量少，且内容和体系不能反映科技发展的水平，不能满足培养人才的需求，为此，我们系统挑选了一批国外经典教材和前沿著作，组织分批出版。图书选择的几个基本原则是：在本领域内广泛采用，有很大影响力；内容反映科技的最新发展，所述内容是本领域的研究热点；编写和体系与国内现有图书差别较大，能对我国微电子教育改革有所启示。本套丛书还侧重于微电子技术的实用性，选取了一批集成电路设计方面的工程技术用书，使读者能方便地应用于实践。 我们真诚地希望，这套丛书能对国内高校师生、工程技术人员以及科研人员的学习和工作有所帮助，对推动我国集成电路的发展有所促进。也衷心期望着广大读者对我们一如既往的关怀和支持，鼓励我们出版更多、更好的图书。
《专用集成电路时序验证》是近10年来惟一一本专门讨论时序及时序验证的专著，共分4章。《专用集成电路时序验证》全面讨论了静态时序验证的各方面内容；全书不仅紧密结合电路图和波形图进行讲解，还结合Synopsys公司的逻辑综合和静态时序分析工具讲解如何通过命令加以实现；介绍过程中不仅从理论上阐述了延迟模型，而且注重实践环节，引入了大量实际示例加以深入探讨。这种写作风格将促进读者能够更全面、细致地理解所讲内容，因此《专用集成电路时序验证》十分适合自学。
内库加（Farzad Nekoogar） is Director of Design Services at SiliconDesigns International. Farzad has extensive practical expe-rience verifying timing ofASICs， FPGAs， and systems-on-a-chip. He is the author of Digital Control Using Digital Sig-nal Processing， published by Prentice Hall PTR. He has lec-tured at the University of California at Berkeley on signalprocessing， control systems， and theoretical physics （specifi-cally， Superstring Theory）. He is currently a lecturer at theDepartment of Applied Science at the University of Califor-nia at Davis. Farzad， seen here in December 1992 at Stanford University， with Sir Roger Penrose.Farzad writes： "In this book we try to solve timing issues related to design of micro-chips. I am honored to be pictured here with Sir Roger Penrose， one of the most bril-liant scientists of all time， who has authored some of the most complex theories aboutspace-time， contributing a lot to our understanding of the universe."
List of FiguresList of TablesPrefaceAcknowledgments1 Introduction to Timing Verification1.1 Introduction1.2 Overview of Timing Verification1.2.1 Intrinsic vs. Extrinsic Delay1.2.2 Path Delay1.3 Interface Timing Analysis2 Elements of Timing Verification2.1 Introduction2.2 Clock Definitions2.2.1 Gated Clocks2.2.2 Clock Skews and Multiple Clock Groups2.2.3 Multifrequency Clocks2.2.4 Multiphase Clocks2.3 More on STA2.3.1 False Paths2.3.2 Multicycle Path Analysis2.3.3 Timing Specifications2.3.4 Timing Checks2.4 Timing Analysis of Phase-Locked Loops2.4.1 PLL Basics2.4.2 PLL Ideal Behavior2.4.3 PLL Errors3 Timing in ASICs3.1 Introduction3.2 Prelayout Timing3.2.1 RTL vs. Gate-Level Timing3.2.2 Timing in RTL Code3.2.3 Delay with a Continuous Assignment Statement3.2.4 Delay in a Process Statement3.2.6 Intra-Assignment Delays3.2.6 The Verilog Specify Block3.2.7 Timing in-Gate Level Code3.2.8 Synthesis and Timing Constraints3.2.9 Design Rule Constraints3.2.10 Optimization ConstrAints3.2.11 Gate and Wire-Load Models3.2.12 The Synthesis Flow3.2.13 Synthesis Tips3.2.14 Back Annotation to Gate-Level RTL3.3 Post. layout Timing3.3.1 Man-A1 Line-Propagation Delay Calculations3.3.2 Signal-Line Capacitance Calculation3.3.3 Signal Line Resistance Calculation3.3.4 Signal Trace RC Delay Evaluation3.4 ASIC Sign-Off Checklist3.4.1 Library Development3.4.2 Functional Specification3.4.3 RTL Coding3.4.4 Simulations of RTL3.4.5 Logic Synthesis3.4.6 Test Insertion and ATPG3.4.7 Postsynthesis Gate-Level Simulation or Static Timing Analysis3.4.8 Floorplsnning3.4.9 Place and Route3.4.10 Final Verification of the Extracted Netlist3.4.11 Mask Generation and Fabrication3.4.12 Testing4 ProgrAmmable Logic Based Design4.1 Introduction4.2 Programmable Logic Structures4.2.1 Logic Block4.2.2 Input/Output Block4.2.3 Routing Facilities4.3 Design Flow4.4 Timing Parameters4.4.1 Timing Derating Factors4.4.2 Grading Programmable Logic Devices by Speed4.4.3 Beet-Case Delay Values4.5 Timing Analysis4.5.1 Actel ACT FPGA Fsmily4.5.2 Actel ACT 3 Architecture4.5.3 Actel ACT 3 Timing Model4.5.4 Altera FLEX 80004.5.5 Altera FLEX 8000 Architecture4.5.6 Altera FLEX 8000 Timing Model4.5.7 Xilinx XC3000/XC4000 FPGA Families4.5.8 Xilinx XC9500 CPLD4.5.9 Xilinx XC9500 CPLD Architecture4.5.10 Xilinx XC9500 CPLD Timing Model4.6 HDL Synthesis4.7 Software Development Systems4.7.1 Timing Constraints4.7.2 Operating Conditions4.7.3 Static Timing Analysis4.7.4 Vendor-Specific Timing-Verification Tools4.7.5 Actel Designer4.7.6 Altera MAX+PLUS II4.7.7 Xilinx XACT/M1A PrimeTimeB PearlC TimingDesignerD Transistor-Level Timing VerificationReferencesIndexAbout the Author
Table 1.3 reveals how the input signals determine which paththrough the circuit drives the output. Whenever the input signal e is ne, the values of the other input signals are irrelevant because theone on input e forces the output of the NOR gate to zero. Essentiallythe same situation occurs on line 2 of Table 1.3. The value on input ddetermines the output value. Line 3 shows the conditions where theoutput depends on input a. Line 4 is a more interesting case becausethe path to the output depends on the order of input signal transi-tions. If the input signals are 00000 then become 10000, the transi-tion goes through path cl-c2-c4-c5-c6. The transition 11000 to 10000takes the c2-c4-c5-c6 path while the 10100 to 10000 transition goesthrough the c3-c4-c5-c6 path. In this circuit, the delays from b-outand c-out are the same, but gate and interconnect delays could bedifferent and change the result. The inputs of lines 5 and 6 activatelogic that forces the paths c-out and b-out respectively to determinethe output value. The slowest path between b-out and c-out deter-mines the delay in line 7 only if the transition is from 10000 to11100. The delay path is already set and possibly settled with transi-tions from 10100 to 11100 （c-out） and 11000 to 11100 （b-out）. As a result of understanding the circuits response to inputstimuli, the timing analyzer knows that every path is capable ofproducing a response at the output, so it must consider all pathswhen determining delay. In this specific case, the longest path isfrom a-out through c 1-c2-c4-c5-c6 and it is traversed during two dif-ferent transitions: lines 3 and 4. In chapter 2 we will consider false paths. False paths are logicpaths that are not synthesized because they are functionallyblocked. These paths are recognized by static timing analyzers asunconstrained paths. One example of false paths is the clocks thatare not harmonically related to each other.
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